K60P100M100SF2RM Datasheet, PDF (492/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
Assuming zero wait states on the system bus, DMA requests can be processed every 9
cycles. Assuming an average of the access times associated with internal peripheral bus-
to-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can
be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle ?
+5. The resulting peak request rate, as a function of the system frequency, is shown in the
following table.
Table 21-295. eDMA peak request rate (MReq/sec)
System frequecy (MHz)
66.6
83.3
100.0
133.3
150.0
Request rate
with zero wait states
7.4
9.2
11.1
14.8
16.6
Request rate
with wait states
5.8
7.2
8.7
11.6
13.0
A general formula to compute the peak request rate with overlapping requests is:
PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ]
where:
PEAKreq
freq
entry
read_ws
write_ws
xit
Table 21-296. Peak request formula legend
Where
Represents
Peak request rate
System frequency
Channel startup (4 cycles)
Wait states seen during the system bus read data phase
Wait states seen during the system bus write data phase
Channel shutdown (3 cycles)
For example, consider a system with the following characteristics:
• Internal SRAM can be accessed with one wait-state when viewed from the system
bus data phase
• All internal peripheral bus reads require two wait-states, and internal peripheral bus
writes three wait-states viewed from the system bus data phase
• System operates at 150 MHz
For an SRAM to internal peripheral bus transfer,
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
492
Freescale Semiconductor, Inc.