K60P100M100SF2RM Datasheet, PDF (1499/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
6
T8
5
TXDIR
4
TXINV
3
ORIE
2
NEIE
1
FEIE
Chapter 51 Universal Asynchronous Receiver/Transmitter (UART)
UARTx_C3 field descriptions (continued)
Transmit Bit 8
Description
T8 is the ninth data bit transmitted when the UART is configured for 9-bit data format (C1[M] = 1) or
(C4[M10] = 1).
NOTE: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.
The same value is transmitted until T8 is rewritten.
Transmitter Pin Data Direction in Single-Wire mode
This bit determines whether the TXD pin is used as an input or output in the single-wire mode of
operation. This bit is relevant only to the single-wire mode. When C7816[ISO7816E] is set/enabled and
C7816[TTYPE] = 1, this bit is automatically cleared after the requested block has been transmitted. This
condition is detected when TL7816[TLEN] = 0 and 4 additional characters have been transmitted.
Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is being transmitted,
the hardware will automatically override this bit as needed. In this situation TXDIR will not reflect the
temporary state associated with the NACK.
0 TXD pin is an input in single-wire mode.
1 TXD pin is an output in single-wire mode.
Transmit Data Inversion.
Setting this bit reverses the polarity of the transmitted data output. In NRZ format, a one is represented by
a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In
IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a
one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining
idle high for a one for inverted polarity. This bit is automatically set or cleared when C7816[INIT] and
C7816[ISO7816E] are enabled and an initial character is detected.
NOTE: Setting TXINV inverts all transmitted values, including idle, break, start, and stop bits. In loop
mode, if TXINV is set, the receiver gets the transmit inversion bit when RXINV is disabled.When
C7816[ISO7816E] is set/enabled then only the transmitted data bits and parity bit are inverted.
0 Transmit data is not inverted.
1 Transmit data is inverted.
Overrun Error Interrupt Enable
This bit enables the overrun error flag (S1[OR]) to generate interrupt requests.
0 OR interrupts are disabled.
1 OR interrupt requests are enabled.
Noise Error Interrupt Enable
This bit enables the noise flag (S1[NF]) to generate interrupt requests.
0 NF interrupt requests are disabled.
1 NF interrupt requests are enabled.
Framing Error Interrupt Enable
This bit enables the framing error flag (S1[FE]) to generate interrupt requests.
0 FE interrupt requests are disabled.
1 FE interrupt requests are enabled.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1499