K60P100M100SF2RM Datasheet, PDF (510/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
22.3.3 Compare Low Register (EWM_CMPL)
The CMPL register is reset to zero after a CPU reset. This provides no minimum time for
the CPU to service the EWM counter.
NOTE
This register can be written only once after a CPU reset.
Writing this register more than once generates a bus transfer
error.
Address: EWM_CMPL is 4006_1000h base + 2h offset = 4006_1002h
Bit
7
6
5
4
3
2
1
0
Read
Write
COMPAREL
Reset
0
0
0
0
0
0
0
0
EWM_CMPL field descriptions
Field
7–0
COMPAREL
Description
To prevent runaway code from changing this field, software should write to this field after a CPU reset
even if the (default) minimum service time is required.
22.3.4 Compare High Register (EWM_CMPH)
The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum of 256
clocks time, for the CPU to service the EWM counter.
NOTE
This register can be written only once after a CPU reset.
Writing this register more than once generates a bus transfer
error.
NOTE
The valid values for CMPH are up to 0xFE because the EWM
counter never expires when CMPH = 0xFF. The expiration
happens only if EWM counter is greater than CMPH.
Address: EWM_CMPH is 4006_1000h base + 3h offset = 4006_1003h
Bit
7
6
5
4
3
2
1
0
Read
Write
COMPAREH
Reset
1
1
1
1
1
1
1
1
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
510
Freescale Semiconductor, Inc.