K60P100M100SF2RM Datasheet, PDF (1023/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

begin
Chapter 39 FlexTimer (FTM)
legacy
PWM synchronization
SYNCMODE
bit ?
=1
enhanced PWM synchronization
FTM counter is reset by
software trigger
1 = _SWRSTCNT = 0
bit ?
SWSYNC
bit ?
=1
software
trigger
end
update FTM counter with
CNTIN register value
update the channels outputs
with their initial value
clear SWSYNC bit
end
FTM counter is reset by
hardware trigger
HWRSTCNT ^{= 1}
bit ?
hardware
trigger
TRIGn ^{= 0}
bit ?
=1
wait hardware trigger n
update FTM counter with
CNTIN register value
update the channels outputs
with their initial value
end
HWTRIGMODE ^{= 1}
bit ?
=0
clear TRIGn bit
end
Figure 39-221. FTM Counter Synchronization Flowchart
In the case of legacy PWM synchronization, the FTM counter synchronization depends
on REINIT and PWMSYNC bits according to the following description.
If (SYNCMODE = 0), (REINIT = 1) and (PWMSYNC = 0) then this synchronization is
made on the next enabled trigger event. If the trigger event was a software trigger then
the SWSYNC bit is cleared according to the following example. If the trigger event was a
hardware trigger then the TRIGn bit is cleared according to Hardware Trigger. Examples
with software and hardware triggers follow.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1023