K60P100M100SF2RM Datasheet, PDF (1399/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 49 SPI (DSPI)
49.3.1 DSPI Module Configuration Register (SPIx_MCR)
Contains bits to configure various attributes associated with DSPI operations. The HALT
and MDIS bits can be changed at any time, but they only take effect on the next frame
boundary. Only the HALT and MDIS bits in the MCR can be changed, while the DSPI is
in the Running state.
Addresses: SPI0_MCR is 4002_C000h base + 0h offset = 4002_C000h
SPI1_MCR is 4002_D000h base + 0h offset = 4002_D000h
SPI2_MCR is 400A_C000h base + 0h offset = 400A_C000h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
DCONF FRZ
W
0
PCSIS[5:0]
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
SMPL_PT
W
CLR_
TXF
CLR_
RXF
Reset 0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SPIx_MCR field descriptions
Field
31
MSTR
Master/Slave Mode Select
Description
Configures the DSPI for either master mode or slave mode.
30
CONT_SCKE
0 DSPI is in slave mode.
1 DSPI is in master mode.
Continuous SCK Enable
Enables the Serial Communication Clock (SCK) to run continuously.
29–28
DCONF
0 Continuous SCK disabled.
1 Continuous SCK enabled.
DSPI Configuration
Selects among the different configurations of the DSPI.
00 SPI
01 Reserved
10 Reserved
11 Reserved
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1399