K60P100M100SF2RM Datasheet, PDF (1683/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 53 Integrated interchip sound (I2S)
Table 53-3. Clock pin configurations (continued)
CR
RCR
TCR
[SYN] RXDIR RFDIR TXDIR TFDIR
0
1
0
1
0
0
1
0
1
1
0
1
1
1
0
0
1
1
1
1
1
0
x
0
0
1
0
x
0
1
1
0
x
1
0
1
0
x
1
1
1
1
x
0
x
1
1
x
1
x
SRCK
STCK
RCK out
TCK out
RCK out
TCK out
RCK out
TCK out
RCK out
TCK out
Synchronous mode
—
CK in
—
CK in
—
CK out
—
CK out
—
Gated in
—
Gated out
SRFS
RFS in
RFS in
RFS out
RFS out
—
—
—
—
—
—
STFS
TFS in
TFS out
TFS in
TFS out
FS in
FS out
FS in
FS out
—
—
53.3 Memory map/register definition
This section consists of register descriptions in address order. Each description includes a
standard register diagram with an associated figure number. Details of register bit and
field function follow the register diagrams in bit order.
Absolute
address
(hex)
I2S memory map
Register name
Width
(in bits)
Access
Reset value
4002_F000 I2S Transmit Data Registers 0 (I2S0_TX0)
32
R/W 0000_0000h
4002_F004 I2S Transmit Data Registers 1 (I2S0_TX1)
32
R/W 0000_0000h
4002_F008 I2S Receive Data Registers 0 (I2S0_RX0)
32
R
0000_0000h
4002_F00C I2S Receive Data Registers 1 (I2S0_RX1)
32
R
0000_0000h
4002_F010 I2S Control Register (I2S0_CR)
32
R/W 0000_0000h
4002_F014 I2S Interrupt Status Register (I2S0_ISR)
32
Table continues on the next page...
R/W 0000_3003h
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1683