K60P100M100SF2RM Datasheet, PDF (495/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 21 Direct Memory Access Controller (eDMA)
The following figure shows how each DMA request initiates one minor-loop transfer, or
iteration, without CPU intervention. DMA arbitration can occur after each minor loop,
and one level of minor loop DMA preemption is allowed. The number of minor loops in
a major loop is specified by the beginning iteration count (BITER).
Source or destination memory
DMA request
Current major
loop iteration
count (CITER)
3
DMA request
2
DMA request
1
Figure 21-292. Example of multiple loop iterations
The following figure lists the memory array terms and how the TCD settings interrelate.
xADDR: (Starting address)
xLAST: Number of bytes added to
current address after major loop
(typically used to loop back)
xSIZE: (size of one
data transfer)
Minor loop
(NBYTES in
minor loop,
often the same
value as xSIZE)
Offset (xOFF): number of bytes added to
current address after each transfer
(often the same value as xSIZE)
Minor loop
Each DMA source (S) and
destination (D) has its own:
Address (xADDR)
Size (xSIZE)
Offset (xOFF)
Modulo (xMOD)
Last Address Adjustment (xLAST)
where x = S or D
Last minor loop
Peripheral queues typically
have size and offset equal
to NBYTES.
Figure 21-293. Memory array terms
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
495