K60P100M100SF2RM Datasheet, PDF (1408/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
SPIx_CTARn_SLAVE field descriptions (continued)
Field
Description
Selects which edge of SCK causes data to change and which edge causes data to be captured. This bit is
used in both master and slave mode. For successful communication between serial devices, the devices
must have identical clock phase settings. In Continuous SCK mode, the bit value is ignored and the
transfers are done as the CPHA bit is set to 1.
24–23
Reserved
22–0
Reserved
0 Data is captured on the leading edge of SCK and changed on the following edge.
1 Data is changed on the leading edge of SCK and captured on the following edge.
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
49.3.5 DSPI Status Register (SPIx_SR)
SR contains status and flag bits. The bits reflect the status of the DSPI and indicate the
occurrence of events that can generate interrupt or DMA requests. Software can clear flag
bits in the SR by writing a 1 to them. Writing a 0 to a flag bit has no effect. This register
may not be writable in module disable mode due to the use of power saving mechanisms.
Addresses: SPI0_SR is 4002_C000h base + 2Ch offset = 4002_C02Ch
SPI1_SR is 4002_D000h base + 2Ch offset = 4002_D02Ch
SPI2_SR is 400A_C000h base + 2Ch offset = 400A_C02Ch
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R TCF
0
0
0
0
0
0
0
0
0
W w1c w1c
w1c w1c
w1c
w1c
w1c
Reset 0
0
0
0
0
0
*
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
TXCTR
TXNXTPTR
RXCTR
POPNXTPTR
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
* Notes:
• TFFF bitfield: Depends on MCR[MDIS] bit. See bit description for more details.
1408
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.