K60P100M100SF2RM Datasheet, PDF (816/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Register Definition
ADCx_SC2 field descriptions (continued)
Field
Description
00 Default voltage reference pin pair (external pins V_REFH and V_REFL)
01 Alternate reference pair (V_ALTH and V_ALTL). This pair may be additional external pins or internal
sources depending on MCU configuration. Consult the Chip Configuration information for details
specific to this MCU.
10 Reserved
11 Reserved
34.3.7 Status and control register 3 (ADCx_SC3)
The SC3 register controls the calibration, continuous convert, and hardware averaging
functions of the ADC module.
Addresses: ADC0_SC3 is 4003_B000h base + 24h offset = 4003_B024h
ADC1_SC3 is 400B_B000h base + 24h offset = 400B_B024h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
CALF
0
CAL
AVGS
Reset 0
Field
31–8
Reserved
7
CAL
6
CALF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADCx_SC3 field descriptions
Description
This read-only field is reserved and always has the value zero.
Calibration
CAL begins the calibration sequence when set. This bit stays set while the calibration is in progress and is
cleared when the calibration sequence is completed. The CALF bit must be checked to determine the
result of the calibration sequence. Once started, the calibration routine cannot be interrupted by writes to
the ADC registers or the results will be invalid and the CALF bit will set. Setting the CAL bit will abort any
current conversion.
Calibration failed flag
CALF displays the result of the calibration sequence. The calibration sequence will fail if ADTRG = 1, any
ADC register is written, or any stop mode is entered before the calibration sequence completes. The
CALF bit is cleared by writing a 1 to this bit.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
816
Freescale Semiconductor, Inc.