K60P100M100SF2RM Datasheet, PDF (865/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
3
IEF
2
CFR
1
CFF
0
COUT
Chapter 35 Comparator (CMP)
CMPx_SCR field descriptions (continued)
0 Interrupt disabled.
1 Interrupt enabled.
Comparator Interrupt Enable Falling
Description
The IEF bit enables the CFF interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFF bit is set.
0 Interrupt disabled.
1 Interrupt enabled.
Analog Comparator Flag Rising
During normal operation, the CFR bit is set when a rising edge on COUT has been detected. The CFR bit
is cleared by writing a logic one to the bit. During Stop modes, CFR can be programmed as either edge or
level sensitive via the SMELB bit.
NOTE: Edge detection during Stop mode is only supported on platforms that allow peripherals to be
clocked during Stop modes. If the CFR flag is active during Stop mode, then SMELB must be set
to 0 for cases where it is not receiving a clock during Stop mode.
0 Rising edge on COUT has not been detected.
1 Rising edge on COUT has occurred.
Analog Comparator Flag Falling
During normal operation, the CFF bit is set when a falling edge on COUT has been detected. The CFF bit
is cleared by writing a logic one to the bit. During Stop modes, CFF can be programmed as either edge or
level sensitive via the SMELB bit.
NOTE: Edge detection during Stop mode is only supported on platforms that allow peripherals to be
clocked during Stop modes. If the CFF flag is active during Stop mode, then SMELB must be set
to 0 for cases where it is not receiving a clock during Stop mode.
0 Falling edge on COUT has not been detected.
1 Falling edge on COUT has occurred.
Analog Comparator Output
Reading the COUT bit will return the current value of the analog comparator output. The register bit is
reset to zero and will read as CR1[INV] when the Analog Comparator module is disabled (CR1[EN] = 0).
Writes to this bit are ignored.
35.7.5 DAC Control Register (CMPx_DACCR)
Addresses: CMP0_DACCR is 4007_3000h base + 4h offset = 4007_3004h
CMP1_DACCR is 4007_3008h base + 4h offset = 4007_300Ch
CMP2_DACCR is 4007_3010h base + 4h offset = 4007_3014h
Bit
7
6
5
4
3
2
1
Read
Write
DACEN
VRSEL
VOSEL
Reset
0
0
0
0
0
0
0
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
0
0
865