K60P100M100SF2RM Datasheet, PDF (184/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Internal clocking requirements
Clock
System clock
Bus clock
FlexBus clock
Flash clock
Option 3:
Clock
Core clock
System clock
Bus clock
FlexBus clock
Flash clock
Frequency
100 MHz
50 MHz
25 MHz
25 MHz
Frequency
96 MHz
96 MHz
48 MHz
48 MHz
24 MHz
5.5.1 Clock divider values after reset
Each clock divider is programmed via the SIM module’s CLKDIVn registers. The flash
memory's FTFL_FOPT[LPBOOT] bit controls the reset value of the core clock, system
clock, bus clock, and flash clock dividers as shown below:
FTFL_FOPT
[LPBOOT]
0
1
Core/system
clock
0x7 (divide by 8)
0x0 (divide by 1)
Bus clock
0x7 (divide by 8)
0x0 (divide by 1)
FlexBus clock Flash clock
Description
0xF (divide by 16) 0xF (divide by 16) Low power boot
0x1 (divide by 2) 0x1 (divide by 2) Fast clock boot
This gives the user flexibility for a lower frequency, low-power boot option. The flash
erased state defaults to fast clocking mode, since where the low power boot
(FTFL_FOPT[LPBOOT]) bit resides in flash is logic 1 in the flash erased state.
To enable the low power boot option program FTFL_FOPT[LPBOOT] to zero. During
the reset sequence, if LPBOOT is cleared, the system is in a slow clock configuration.
Upon any system reset, the clock dividers return to this configurable reset state.
5.5.2 VLPR mode clocking
The clock dividers cannot be changed while in VLPR mode. They must be programmed
prior to entering VLPR mode to guarantee:
• the core/system, FlexBus, and bus clocks are less than or equal to 2 MHz, and
• the flash memory clock is less than or equal to 1 MHz
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
184
Freescale Semiconductor, Inc.