K60P100M100SF2RM Datasheet, PDF (286/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)
Address: SIM_SCGC3 is 4004_7000h base + 1030h offset = 4004_8030h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SIM_SCGC3 field descriptions
Field
31
Reserved
30
Reserved
29–28
Reserved
27
ADC1
Description
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
ADC1 Clock Gate Control
This bit controls the clock gate to the ADC1 module.
26–25
Reserved
24
FTM2
0 Clock disabled
1 Clock enabled
This read-only field is reserved and always has the value zero.
FTM2 Clock Gate Control
This bit controls the clock gate to the FTM2 module.
23–18
Reserved
17
SDHC
0 Clock disabled
1 Clock enabled
This read-only field is reserved and always has the value zero.
SDHC Clock Gate Control
This bit controls the clock gate to the SDHC module.
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
286
Freescale Semiconductor, Inc.