K60P100M100SF2RM Datasheet, PDF (1714/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
I2Sx_ACADD field descriptions
Field
31–19
Reserved
18–0
ACADD
Description
This read-only field is reserved and always has the value zero.
AC97 Command Address.
These bits store the Command Address Slot information (bit 19 of the slot is sent in accordance with the
Read and Write Command bits in ACNT register). These bits can be updated by a direct write from the
Core. They are also updated with the information received in the incoming Command Address Slot. If the
contents of these bits change due to an update, the CMDAU bit in ISR is set.
53.3.15 I²S AC97 Command Data Register (I2Sx_ACDAT)
Addresses: I2S0_ACDAT is 4002_F000h base + 40h offset = 4002_F040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
ACDAT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_ACDAT field descriptions
Field
31–20
Reserved
19–0
ACDAT
Description
This read-only field is reserved and always has the value zero.
AC97 Command Data.
The outgoing Command Data Slot carries the information contained in these bits. These bits can be
updated by a direct write from the Core. They are also updated with the information received in the
incoming Command Data Slot. If the contents of these bits change due to an update, the CMDDU bit in
ISR is set. These bits are transmitted only during AC97 Write Command. During AC97 Read Command,
0x00000 is transmitted in time slot #2.
53.3.16 I²S AC97 Tag Register (I2Sx_ATAG)
Addresses: I2S0_ATAG is 4002_F000h base + 44h offset = 4002_F044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
ATAG
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1714
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.