K60P100M100SF2RM Datasheet, PDF (1579/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
20
CICEN
19
CCCEN
18
Reserved
17–16
RSPTYP
15–6
Reserved
5
MSBSEL
4
DTDSEL
Chapter 52 Secured digital host controller (SDHC)
SDHC_XFERTYP field descriptions (continued)
Description
This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. It is set to 0
for the following:
• Commands using only the CMD line (for example: CMD52).
• Commands with no data transfer, but using the busy signal on DAT[0] line (R1b or R5b, for
example: CMD38).
NOTE: In resume command, this bit shall be set, and other bits in this register shall be set the same as
when the transfer was initially launched. When the Write Protect switch is on, (i.e. the WPSPL bit
is active as ‘0’), any command with a write operation will be ignored. That is to say, when this bit
is set, while the DTDSEL bit is 0, writes to the register Transfer Type are ignored.
0b No data present
1b Data present
Command Index Check Enable
If this bit is set to 1, the SDHC will check the index field in the response to see if it has the same value as
the command index. If it is not, it is reported as a command index error. If this bit is set to 0, the index field
is not checked.
0b Disable
1b Enable
Command CRC Check Enable
If this bit is set to 1, the SDHC shall check the CRC field in the response. If an error is detected, it is
reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked. The number of bits
checked by the CRC field value changes according to the length of the response.
0b Disable
1b Enable
This read-only field is reserved and always has the value zero.
Response Type Select
00b No response
01b Response length 136
10b Response length 48
11b Response length 48, check busy after response
This read-only field is reserved and always has the value zero.
Multi/Single Block Select
This bit enables multiple block DAT line data transfers. For any other commands, this bit shall be set to 0.
If this bit is 0, it is not necessary to set the block count register.
0b Single block
1b Multiple blocks
Data Transfer Direction Select
This bit defines the direction of DAT line data transfers. The bit is set to 1 by the host driver to transfer
data from the SD card to the SDHC and is set to 0 for all other commands.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1579