K60P100M100SF2RM Datasheet, PDF (1040/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
CNTIN = 0x0000
MOD = 0x000F
CPWMS = 0
system clock
FTM counter
0x00
0x01 0x02 0x03 0x04 0x05
CLKS[1:0] bits
00
01
initialization trigger
Figure 39-242. Initialization Trigger Is Generated If (CNT = CNTIN), (CLKS[1:0] = 0:0), and
a Value Different From Zero Is Written to CLKS[1:0] Bits
The initialization trigger output provides a trigger signal that is used for on-chip modules.
Note
It is expected that the initialization trigger be used only in
combine mode.
39.4.22 Capture Test Mode
The capture test mode allows to test the CnV registers, the FTM counter and the
interconnection logic between the FTM counter and CnV registers.
In this test mode, all channels must be configured for input capture mode (Input Capture
Mode) and FTM counter must be configured to the up counting (Up Counting).
When the capture test mode is enabled (CAPTEST = 1), the FTM counter is frozen and
any write to CNT register updates directly the FTM counter (see the following figure).
After it was written, all CnV registers are updated with the written value to CNT register
and CHnF bits are set. Therefore, the FTM counter is updated with its next value
according to its configuration (its next value depends on CNTIN, MOD, and the written
value to FTM counter).
The next reads of CnV registers return the written value to the FTM counter and the next
reads of CNT register return FTM counter next value.
1040
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.