K60P100M100SF2RM Datasheet, PDF (1421/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

49.4.2.4.1 Filling the TX FIFO
Chapter 49 SPI (DSPI)
Host software or other intelligent blocks can add (push) entries to the TX FIFO by
writing to the PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) in
the SR is set. The TFFF bit is cleared when TX FIFO is full and the DMA controller
indicates that a write to PUSHR is complete. Writing a '1' to the TFFF bit also clears it.
The TFFF can generate a DMA request or an interrupt request. See Transmit FIFO Fill
Interrupt or DMA Request for details.
The DSPI ignores attempts to push data to a full TX FIFO, the state of the TX FIFO does
not change and no error condition is indicated.
49.4.2.4.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift
register. Entries are transferred from the TX FIFO to the shift register and shifted out as
long as there are valid entries in the TX FIFO. Every time an entry is transferred from the
TX FIFO to the shift register, the TX FIFO Counter decrements by one. At the end of a
transfer, the TCF bit in the SR is set to indicate the completion of a transfer. The TX
FIFO is flushed by writing a '1' to the CLR_TXF bit in MCR.
If an external bus master initiates a transfer with a DSPI slave while the slave's DSPI TX
FIFO is empty, the Transmit FIFO Underflow Flag (TFUF) in the slave's SR is set. See
Transmit FIFO Underflow Interrupt Request for details.
49.4.2.5 Receive First In First Out (RX FIFO) Buffering Mechanism
The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds
4 received SPI data frames. The number of entries in the RX FIFO is device-specific. SPI
data is added to the RX FIFO at the completion of a transfer when the received data in the
shift register is transferred into the RX FIFO. SPI data are removed (popped) from the
RX FIFO by reading the DSPI POP RX FIFO Register (POPR). RX FIFO entries can
only be removed from the RX FIFO by reading the POPR or by flushing the RX FIFO.
The RX FIFO Counter field (RXCTR) in the DSPI Status Register (SR) indicates the
number of valid entries in the RX FIFO. The RXCTR is updated every time the POPR is
read or SPI data is copied from the shift register to the RX FIFO.
The POPNXTPTR field in the SR points to the RX FIFO entry that is returned when the
POPR is read. The POPNXTPTR contains the positive offset from RXFR0 in number of
32-bit registers. For example, POPNXTPTR equal to two means that the RXFR2 contains
the received SPI data that will be returned when POPR is read. The POPNXTPTR field is
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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