K60P100M100SF2RM Datasheet, PDF (136/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Timers
3.8.3.1 PIT/DMA Periodic Trigger Assignments
The PIT generates periodic trigger events to the DMA Mux as shown in the table below.
Table 3-58. PIT channel assignments for periodic DMA triggering
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel Number
PIT Channel 0
PIT Channel 1
PIT Channel 2
PIT Channel 3
PIT Channel
3.8.3.2 PIT/ADC Triggers
PIT triggers are selected as ADCx trigger sources using the SOPT7[ADCxTRGSEL] bits
in the SIM module. For more details, refer to SIM chapter.
3.8.4 Low-power timer configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge
Register
access
Low-power timer
Module signals
Topic
Full description
System memory map
Clocking
Figure 3-48. LPT configuration
Table 3-59. Reference links to related information
Related module
Low-power timer
Reference
Low-power timer
System memory map
Clock Distribution
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
136
Freescale Semiconductor, Inc.