K60P100M100SF2RM Datasheet, PDF (1532/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
• After every start bit.
• After the receiver detects a data bit change from logic 1 to logic 0 (after the majority
of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of
the next RT8, RT9, and RT10 samples returns a valid logic 0).
To locate the start bit, data recovery logic does an asynchronous search for a logic 0
preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT
clock begins to count to 16.
START BIT
LSB
Rx pin input
SAMPLES 1 1 1 1 1 1 1 1 0
0
0
0000
START BIT
QUALIFICATION
START BIT
DATA
VERIFICATION SAMPLING
RT CLOCK
RT CLOCK COUNT
RESET RT CLOCK
Figure 51-190. Receiver data sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5,
and RT7 when C7816[ISO_7816E] is cleared/disabled and RT8, RT9 and RT10 when
C7816[ISO_7816E] is set/enabled. The following table summarizes the results of the start
bit verification samples.
Table 51-196. Start bit verification
RT3, RT5, and RT7 samples
RT8, RT9, RT10 samples when 7816E
000
001
010
011
100
101
110
111
Start bit verification
Yes
Yes
Yes
No
Yes
No
No
No
Noise flag
0
1
1
0
1
0
0
0
If start bit verification is not successful, the RT clock is reset and a new search for a start
bit begins.
1532
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.