K60P100M100SF2RM Datasheet, PDF (1373/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 48 CAN (FlexCAN)
Clearing one of those three flags does not affect the state of the other two.
An interrupt is generated if an IFLAG bit is asserted and the corresponding mask bit is
asserted too.
A powerful filtering scheme is provided to accept only frames intended for the target
application, thus reducing the interrupt servicing work load. The filtering criteria is
specified by programming a table of up to 128 32-bit registers, according to
CTRL2[RFFN] setting, that can be configured to one of the following formats (see also
Rx FIFO Structure):
• Format A: 128 IDAFs (extended or standard IDs including IDE and RTR)
• Format B: 256 IDAFs (standard IDs or extended 14-bit ID slices including IDE and
RTR)
• Format C: 512 IDAFs (standard or extended 8-bit ID slices)
Note
A chosen format is applied to all entries of the filter table. It is
not possible to mix formats within the table.
Every frame available in the FIFO has a corresponding IDHIT (Identifier Acceptance
Filter Hit Indicator) that can be read by accessing the RXFIR register. The
RXFIR[IDHIT] field refers to the message at the output of the FIFO and is valid while
the IFLAG[BUF5I] flag is asserted. The RXFIR register must be read only before
clearing the flag, which guarantees that the information refers to the correct frame within
the FIFO.
Up to thirty two elements of the filter table are individually affected by the Individual
Mask Registers (RXIMRx), according to the setting of CTRL2[RFFN], allowing very
powerful filtering criteria to be defined. If the IRMQ bit is negated, then the FIFO filter
table is affected by RXFGMASK.
48.4.8 CAN Protocol Related Features
This section describes the CAN protocol related features.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1373