K60P100M100SF2RM Datasheet, PDF (765/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU)
Register
File
CA0-CA3
CAx
CAA
Hash
DES /
AES Row
ALU
Result
Operand1
Command
Go
Decode
Datapath
Control
Figure 32-2. Top Level CAU Block Diagram
32.3 Overview
As the name suggests, the MMCAU provides a mechanism for memory-mapped register
reads and writes to be transformed into specific commands and operands sent to the CAU
coprocessor.
The MMCAU translator module performs all the required control functions affecting the
transmission of commands to the CAU module and, if needed, stalling the PPB
transactions based on the state of the 4-entry command/data FIFO, etc. The translator also
performs some basic integrity checks on PPB operations.
The set of implemented algorithms provides excellent support for network security
standards (SSL, IPsec). Additionally, using the MMCAU efficiently permits the
implementation of any higher level functions or modes of operation (HMAC, CBC, etc.)
based on the supported algorithms.
The cryptographic algorithms are implemented partially in software with only functions
critical to increasing performance implemented in hardware. The MMCAU allows for
efficient, fine-grained partitioning of functions between hardware and software:
• Implement the innermost security kernel functions using the coprocessor instructions
• Implement higher-level functions in software by using the standard processor
instructions
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
765