K60P100M100SF2RM Datasheet, PDF (1452/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map and Register Descriptions
I2Cx_S field descriptions (continued)
Field
Description
0 Acknowledge signal was received after the completion of one byte of data transmission on the bus
1 No acknowledge signal detected
50.3.5 I2C Data I/O register (I2Cx_D)
Addresses: I2C0_D is 4006_6000h base + 4h offset = 4006_6004h
I2C1_D is 4006_7000h base + 4h offset = 4006_7004h
Bit
7
6
5
4
3
2
1
0
Read
Write
DATA
Reset
0
0
0
0
0
0
0
0
I2Cx_D field descriptions
Field
7–0
DATA
Data
Description
In master transmit mode, when data is written to this register, a data transfer is initiated. The most
significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte
of data.
NOTE: When making the transition out of master receive mode, switch the I2C mode before reading the
Data register to prevent an inadvertent initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match occurs.
The C1[TX] bit must correctly reflect the desired direction of transfer in master and slave modes for the
transmission to begin. For example, if the I2C module is configured for master transmit but a master
receive is desired, reading the Data register does not initiate the receive.
Reading the Data register returns the last byte received while the I2C module is configured in master
receive or slave receive mode. The Data register does not reflect every byte that is transmitted on the I2C
bus, and neither can software verify that a byte has been written to the Data register correctly by reading
it back.
In master transmit mode, the first byte of data written to the Data register following assertion of MST (start
bit) or assertion of RSTA (repeated start bit) is used for the address transfer and must consist of the
calling address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
1452
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.