K60P100M100SF2RM Datasheet, PDF (833/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 34 Analog-to-Digital Converter (ADC)
• The MCU is reset or enters Low Power Stop modes.
• The MCU enters Normal Stop mode with ADACK not enabled.
When a conversion is aborted, the contents of the data registers, Rn, are not altered. The
data registers continue to be the values transferred after the completion of the last
successful conversion. If the conversion was aborted by a reset or Low Power Stop
modes, RA and R n return to their reset states.
34.4.5.4 Power control
The ADC module remains in its idle state until a conversion is initiated. If ADACK is
selected as the conversion clock source, but the asynchronous clock output is disabled
(ADACKEN=0), the ADACK clock generator also remains in its idle state (disabled)
until a conversion is initiated. If the asynchronous clock output is enabled
(ADACKEN=1), it remains active regardless of the state of the ADC or the MCU power
mode.
Power consumption when the ADC is active can be reduced by setting ADLPC. This
results in a lower maximum value for f_ADCK .
34.4.5.5 Sample time and total conversion time
For short sample (ADLSMP=0), there is a 2-cycle adder for first conversion over the base
sample time of 4 ADCK cycles. For high speed conversions (ADHSC=1), there is an
additional 2-cycle adder on any conversion. The table below summarizes sample times
for the possible ADC configurations.
ADLSMP
0
1
1
1
1
0
1
1
1
ADC Configuration
ADLSTS
X
00
01
10
11
X
00
01
10
ADHSC
0
0
0
0
0
1
1
1
1
Sample time (ADCK cycles)
First or Single
Subsequent
6
4
24
16
10
6
8
6
26
18
12
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
833