K60P100M100SF2RM Datasheet, PDF (1434/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
49.4.7.1 End of Queue Interrupt Request
The End of Queue Request indicates that the end of a transmit queue is reached. The End
of Queue Request is generated when the EOQ bit in the executing SPI command is set
and the EOQF_RE bit in the RSER is set.
NOTE
This interrupt request is generated when the last bit of the SPI
frame with EOQ bit set is transmitted.
49.4.7.2 Transmit FIFO Fill Interrupt or DMA Request
The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit
FIFO Fill Request is generated when the number of entries in the TX FIFO is less than
the maximum number of possible entries, and the TFFF_RE bit in the RSER is set. The
TFFF_DIRS bit in the RSER selects whether a DMA request or an interrupt request is
generated.
NOTE
TFFF flag clears automatically when DMA is used to fill
TXFIFO.
To clear TFFF when not using DMA, follow these steps for
every PUSH performed using CPU to fill TXFIFO:
1. Wait until TFFF = 1
2. Write data to PUSHR using CPU.
3. Clear TFFF by writing a 1 to its location. If FIFO is not
full, this flag will not clear.
49.4.7.3 Transfer Complete Interrupt Request
The Transfer Complete Request indicates the end of the transfer of a serial frame. The
Transfer Complete Request is generated at the end of each frame transfer when the
TCF_RE bit is set in the RSER.
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.