K60P100M100SF2RM Datasheet, PDF (1323/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
9–8
Reserved
7
SMP
6
BOFFREC
5
TSYN
4
LBUF
3
LOM
Chapter 48 CAN (FlexCAN)
CANx_CTRL1 field descriptions (continued)
Description
This bit provides a mask for the Rx Warning Interrupt associated with the RWRNINT flag in the Error and
Status Register. This bit is read as zero when MCR[WRNEN] bit is negated. This bit can only be written if
MCR[WRNEN] bit is asserted.
0 Rx Warning Interrupt disabled
1 Rx Warning Interrupt enabled
This read-only field is reserved and always has the value zero.
CAN Bit Sampling
This bit defines the sampling mode of CAN bits at the Rx input. This bit can only be written in Freeze
mode as it is blocked by hardware in other modes.
0 Just one sample is used to determine the bit value.
1 Three samples are used to determine the value of the received bit: the regular one (sample point) and
2 preceding samples; a majority rule is used.
Bus Off Recovery
This bit defines how FlexCAN recovers from Bus Off state. If this bit is negated, automatic recovering from
Bus Off state occurs according to the CAN Specification 2.0B. If the bit is asserted, automatic recovering
from Bus Off is disabled and the module remains in Bus Off state until the bit is negated by the user. If the
negation occurs before 128 sequences of 11 recessive bits are detected on the CAN bus, then Bus Off
recovery happens as if the BOFFREC bit had never been asserted. If the negation occurs after 128
sequences of 11 recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for 11
recessive bits before joining the bus. After negation, the BOFFREC bit can be re-asserted again during
Bus Off, but it will only be effective the next time the module enters Bus Off. If BOFFREC was negated
when the module entered Bus Off, asserting it during Bus Off will not be effective for the current Bus Off
recovery.
0 Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
1 Automatic recovering from Bus Off state disabled
Timer Sync
This bit enables a mechanism that resets the free-running timer each time a message is received in
Message Buffer 0. This feature provides means to synchronize multiple FlexCAN stations with a special
“SYNC” message (i.e., global network time). If the RFEN bit in MCR is set (Rx FIFO enabled), the first
available Mailbox, according to CTRL2[RFFN] setting, is used for timer synchronization instead of MB0.
This bit can only be written in Freeze mode as it is blocked by hardware in other modes.
0 Timer Sync feature disabled
1 Timer Sync feature enabled
Lowest Buffer Transmitted First
This bit defines the ordering mechanism for Message Buffer transmission. When asserted, the LPRIOEN
bit does not affect the priority arbitration. This bit can only be written in Freeze mode as it is blocked by
hardware in other modes.
0 Buffer with highest priority is transmitted first.
1 Lowest number buffer is transmitted first.
Listen-Only Mode
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1323