K60P100M100SF2RM Datasheet, PDF (837/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Variable
HSCAdder
Chapter 34 Analog-to-Digital Converter (ADC)
Table 34-113. Typical conversion time (continued)
Time
0
The resulting conversion time is generated using the parameters listed in the preceding
table. Therefore, for bus clock equal to 8 MHz and ADCK equal to 1 MHz, the resulting
conversion time is 57.625 µs (AverageNum). This results in a total conversion time of
1.844 ms.
34.4.5.6.3 Short conversion time configuration
A configuration for short ADC conversion is: 8-bit single ended mode with the bus clock
selected as the input clock source, the input clock divide-by-1 ratio selected, a bus
frequency of 20 MHz, long sample time disabled, and high speed conversion enabled.
The conversion time for this conversion is calculated by using Figure 34-95 and the
information provided in Table 34-107 through Table 34-111. The table below list the
variables of Figure 34-95.
Table 34-114. Typical conversion time
Variable
SFCAdder
AverageNum
BCT
LSTAdder
HSCAdder
Time
5 ADCK cycles + 5 bus clock cycles
1
17 ADCK cycles
0 ADCK cycles
2
The resulting conversion time is generated using the parameters listed in in the preceding
table. Therefore, for bus clock equal to 20 MHz and ADCK equal to 20 MHz, the
resulting conversion time is 1.45 µs.
34.4.5.7 Hardware average function
The hardware average function can be enabled (AVGE=1) to perform a hardware average
of multiple conversions. The number of conversions is determined by the AVGS[1:0]
bits, which select 4, 8, 16, or 32 conversions to be averaged. While the hardware average
function is in progress, the ADACT bit will be set.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
837