K60P100M100SF2RM Datasheet, PDF (1726/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
CLK
FS
TX
DATA 0x5E
REG
STXD
0x5E
TDE
TUE
SRXD
0x55
RX
DATA
REG
RDR
0xD6
0x5E
0xD6
0xD6
0x7B
0xD6
0x7B
0x5E
0xD6
0x12
0x34
$7B
0x55
0x5E
0xD6
0x12
ROE
Note: Processor must write ‘1’ to the corresponding TUE/ROE Interrupt status bit in ISR to clear TUE/ROE Interrupt
Figure 53-49. Network mode timing - continuous clock
53.4.1.3 Gated clock mode
Gated clock mode often connects to SPI-type interfaces on microcontroller units (MCUs)
or external peripheral devices. In gated clock mode, the presence of the clock indicates
that valid data is on the STXD or SRXD signals. For this reason, no frame sync is needed
in this mode. After transmission of data completes, the clock is pulled to the inactive
state. Gated clocks are allowed for the transmit and receive sections with either internal
or external clock in normal mode. Gated clocks are not allowed in network mode. See
Table 53-3 for I²S configuration for gated-mode operation.
The clock operates when the CR[TE] bit and/or the CR[RE] bit are appropriately enabled.
For the case of internally generated clock, all internal bit clocks, word clocks, and frame
clocks continue to operate. When a valid time slot occurs (such as the first time slot in
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.