K60P100M100SF2RM Datasheet, PDF (11/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Section Number
Title
Page
11.4.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................263
11.4.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................263
11.4.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................264
11.4.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................265
11.4.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................265
11.5 Functional description...................................................................................................................................................266
11.5.1 Pin control....................................................................................................................................................266
11.5.2 Global pin control........................................................................................................................................266
11.5.3 External interrupts........................................................................................................................................267
11.5.4 Digital filter..................................................................................................................................................268
Chapter 12
System integration module (SIM)
12.1 Introduction...................................................................................................................................................................269
12.1.1 Features........................................................................................................................................................269
12.1.2 Modes of operation......................................................................................................................................269
12.1.3 SIM Signal Descriptions..............................................................................................................................270
12.2 Memory map and register definition.............................................................................................................................270
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................272
12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................274
12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................276
12.2.4 System Options Register 5 (SIM_SOPT5)..................................................................................................279
12.2.5 System Options Register 6 (SIM_SOPT6)..................................................................................................280
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................281
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................283
12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................284
12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................285
12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................286
12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................287
12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................290
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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