K60P100M100SF2RM Datasheet, PDF (707/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 29 External Bus Interface (FlexBus)
• Chip-select mask registers (CSMRn) provide 16-bit address masking and access
control.
• Chip-select control registers (CSCRn) provide port size and burst capability
indication, wait-state generation, address setup and hold times, and automatic
acknowledge generation features.
29.4.1.1 General Chip-Select Operation
When a bus cycle is routed to the FlexBus, the device first compares its address with the
base address and mask configurations programmed for chip-selects 0 to 5 (configured in
CSCRn). The results depend on if the address matches or not as shown in the following
table.
Table 29-26. Results of Address Comparison
Address Matches
CSARn?
Yes,
one CSAR
Result
The appropriate chip-select is asserted, generating a FlexBus bus cycle as defined in the chip-
select control register.
If CSMR[WP] is set and a write access is performed, the internal bus cycle terminates with a bus
error, no chip select is asserted, and no external bus cycle is performed.
No
Yes,
multiple CSARs
The access is terminated with a bus error response, no chip select is asserted and no FlexBus
cycle is performed.
The access is terminated with a bus error response, no chip select is asserted and no FlexBus
cycle is performed.
29.4.1.2 8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. The processor
always drives a 32-bit address on the FB_AD bus regardless of the external device's
address size. The external device must connect its address/data lines as follows:
• Address lines
• FB_AD from FB_AD0 upward
• Data lines
• If CSCR[BLS] = 0, FB_AD from FB_AD31 downward
• If CSCR[BLS] = 1, FB_AD from FB_AD0 upward
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
707