K60P100M100SF2RM Datasheet, PDF (1343/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
22–16
MBCRC
15
Reserved
14–0
TXCRC
Chapter 48 CAN (FlexCAN)
CANx_CRCR field descriptions (continued)
CRC Mailbox
Description
This field indicates the number of the Mailbox corresponding to the value in TXCRC field.
This read-only field is reserved and always has the value zero.
CRC Transmitted
This field indicates the CRC value of the last message transmitted. This field is updated at the same time
the Tx Interrupt Flag is asserted.
48.3.17 Rx FIFO Global Mask Register (CANx_RXFGMASK)
This register is located in RAM.
If Rx FIFO is enabled RXFGMASK is used to mask the Rx FIFO ID Filter Table
elements that do not have a corresponding RXIMR according to CTRL2[RFFN] field
setting.
This register can only be written in Freeze mode as it is blocked by hardware in other
modes.
Addresses: CAN0_RXFGMASK is 4002_4000h base + 48h offset = 4002_4048h
CAN1_RXFGMASK is 400A_4000h base + 48h offset = 400A_4048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FGM[31:0]
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CANx_RXFGMASK field descriptions
Field
31–0
FGM[31:0]
Rx FIFO Global Mask Bits
Description
These bits mask the ID Filter Table elements bits in a perfect alignment.
The following table shows how the FGM bits correspond to each IDAF field.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1343