K60P100M100SF2RM Datasheet, PDF (293/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
24
FTM0
23
PIT
22
PDB
21
USBDCD
20–19
Reserved
18
CRC
17–16
Reserved
15
I2S
14
Reserved
13
SPI1
Chapter 12 System integration module (SIM)
SIM_SCGC6 field descriptions (continued)
FTM0 Clock Gate Control
Description
This bit controls the clock gate to the FTM0 module.
0 Clock disabled
1 Clock enabled
PIT Clock Gate Control
This bit controls the clock gate to the PIT module.
0 Clock disabled
1 Clock enabled
PDB Clock Gate Control
This bit controls the clock gate to the PDB module.
0 Clock disabled
1 Clock enabled
USB DCD Clock Gate Control
This bit controls the clock gate to the USB DCD module.
0 Clock disabled
1 Clock enabled
This read-only field is reserved and always has the value zero.
CRC Clock Gate Control
This bit controls the clock gate to the CRC module.
0 Clock disabled
1 Clock enabled
This read-only field is reserved and always has the value zero.
I2S Clock Gate Control
This bit controls the clock gate to the I²S module.
0 Clock disabled
1 Clock enabled
This read-only field is reserved and always has the value zero.
SPI1 Clock Gate Control
This bit controls the clock gate to the SPI1 module.
0 Clock disabled
1 Clock enabled
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
293