K60P100M100SF2RM Datasheet, PDF (1681/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

I2S
STXD
SRXD
STCK
STFS
SRCK
SRFS
Chapter 53 Integrated interchip sound (I2S)
I2S internal continuous clock for TX/RX (RCR[RXDIR] = 1,TCR[TXDIR] = 1,
RCR[RFDIR] = 1,TCR[TFDIR] = 1, CR[SYN] = 0)
I2S
STXD
SRXD
STCK
STFS
SRCK
SRFS
I2S external continuous clock for TX/RX (RCR[RXDIR] = 0,TCR[TXDIR] = 0,
RCR[RFDIR] = 0,TCR[TFDIR] = 0, CR[SYN] = 0)
I2S
STXD
SRXD
STCK
STFS
SRCK
SRFS
I2S internal continuous clock for RX (RCR[RXDIR] = 1, TCR[TXDIR] = 0,
RCR[RFDIR] = 1,TCR[TFDIR] = 0, CR[SYN] = 0)
I2S external continuous clock for TX
I2S
STXD
SRXD
STCK
STFS
SRCK
SRFS
I2S internal continuous clock for TX (RCR[RXDIR] = 0, TCR[TXDIR] = 1,
RCR[RFDIR] = 0, TCR[TFDIR] = 1, CR[SYN] = 0)
I2S external continuous clock for RX
Figure 53-2. Asynchronous (SYN = 0) I²S configurations—continuous clock
The following figure shows an example of the port signals for an 8-bit data transfer.
Continuous and gated clock signals are shown, as well as the bit-length frame sync signal
and the word-length frame sync signal.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1681