K60P100M100SF2RM Datasheet, PDF (1016/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
39.4.11.5 CNTIN Register Synchronization
The CNTIN register synchronization updates the CNTIN register with its buffer value.
This synchronization is enabled if (FTMEN = 1), (SYNCMODE = 1) and (CNTINC = 1).
The CNTIN register synchronization can be done only by the enhanced PWM
synchronization (SYNCMODE = 1). The synchronization mechanism is the same as the
MOD register synchronization done by the enhanced PWM synchronization (MOD
Register Synchronization).
39.4.11.6 C(n)V and C(n+1)V Register Synchronization
The C(n)V and C(n+1)V registers synchronization updates the C(n)V and C(n+1)V
registers with their buffer values.
This synchronization is enabled if (FTMEN = 1) and (SYNCEN = 1). The
synchronization mechanism is the same as the MOD register synchronization (MOD
Register Synchronization). However, it is expected that the C(n)V and C(n+1)V registers
be synchronized only by the enhanced PWM synchronization (SYNCMODE = 1).
39.4.11.7 OUTMASK Register Synchronization
The OUTMASK register synchronization updates the OUTMASK register with its buffer
value.
The OUTMASK register can be updated at each rising edge of system clock
(SYNCHOM = 0), by the enhanced PWM synchronization (SYNCHOM = 1 and
SYNCMODE = 1) or by the legacy PWM synchronization (SYNCHOM = 1 and
SYNCMODE = 0). However, it is expected that the OUTMASK register be synchronized
only by the enhanced PWM synchronization.
In the case of enhanced PWM synchronization, the OUTMASK register synchronization
depends on SWOM and HWOM bits. See the following flowchart:
1016
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.