K60P100M100SF2RM Datasheet, PDF (1464/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver
sees an I2C interrupt. User software must ensure that for this interrupt, the contents of the
Data register are ignored and not treated as valid data.
50.4.2.2 Master-Receiver Addresses a Slave-Transmitter
The transfer direction is changed after the second R/W bit. Up to and including
acknowledge bit A2, the procedure is the same as that described for a master-transmitter
addressing a slave-receiver. After the repeated START condition (Sr), a matching slave
remembers that it was addressed before. This slave then checks whether the first seven
bits of the first byte of the slave address following Sr are the same as they were after the
START condition (S), and it tests whether the eighth (R/W) bit is 1. If there is a match,
the slave considers that it has been addressed as a transmitter and generates acknowledge
A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or a
repeated START condition (Sr) followed by a different slave address.
After a repeated START condition (Sr), all other slave devices also compare the first
seven bits of the first byte of the slave address with their own addresses and test the
eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit
devices), or the 11110XX slave address (for 7-bit devices) does not match.
Table 50-43. Master-Receiver Addresses a Slave-Transmitter with a 10-bit
Address
S Slave R/W A1 Slave A2 Sr Slave R/W A3 Data A
...
Data A P
address 0
address
address 1
first 7
second
first 7
bits
byte
bits
11110
AD[8:1]
11110
+ AD10
+ AD10
+ AD9
+ AD9
After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter
sees an I2C interrupt. User software must ensure that for this interrupt, the contents of the
Data register are ignored and not treated as valid data.
50.4.3 Address Matching
All received addresses can be requested in 7-bit or 10-bit address format. The Address
Register 1, which contains the I2C primary slave address, always participates in the
address matching process. If the GCAEN bit is set, general call participates the address
matching process. If the ALERTEN bit is set, alert response participates the address
matching process. If the SIICAEN bit is set, the Address Register 2 participates in the
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.