K60P100M100SF2RM Datasheet, PDF (1688/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
I2Sx_CR field descriptions (continued)
Field
Description
This bit provides the option to keep the frame-sync and clock enabled or to disable them after the receive
frame in which the receiver is disabled. Writing to this bit has effect only when CR[RE] is disabled.The
receiver is disabled by clearing the CR[RE] bit.
10
TFRCLKDIS
0 Continue frame-sync/clock generation after current frame during which CR[RE] is cleared. This may
be required when Frame-sync and Clocks are required from I²S, even when no data is to be received.
1 Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where
receiver is already disabled in current or previous frames.
Transmit Frame Clock Disable.
This bit provide option to keep the frame-sync and clock enabled or disabled after current transmit frame,
in which transmitter is disabled by clearing CR[TE] bit. Writing to this bit has effect only when I²S is
enabled CR[TE] is disabled.
9
CLKIST
0 Continue frame-sync/clock generation after current frame during which CR[TE] is cleared. This may
be required when frame-sync and clocks are required from I²S, even when no data is to be received.
1 Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where
transmitter is already disabled in current or previous frames.
Clock Idle State.
This bit controls the idle state of the transmit clock port during I²S internal gated mode. Note: When Clock
idle state is `1' the clock polarity should always be negedge triggered and when clock idle = `0' the clock
polarity should always be positive edge triggered.
8
TCHEN
0 Clock idle state is `0'.
1 Clock idle state is `1'.
Two-Channel Operation Enable.
This bit allows I²S to operate in the two-channel mode.In this mode while receiving, the RXSR transfers
data to RX0 and RX1 alternately and while transmitting, data is alternately transferred from TX0 and TX1
to TXSR. For an even number of slots, two-channel operation can be enabled to optimize usage of both
FIFOs or disabled as in the case of odd number of active slots. This feature is especially useful in I2S
mode, where data for left speaker can be placed in Tx-FIFO0 and for right speaker in Tx-FIFO1.
7
SYSCLKEN
0 Two-channel mode disabled.
1 Two-channel mode enabled.
System Clock (Oversampling Clock) Enable.
When set, this bit allows the I²S to output the (network clock) at the SRCK port, provided that
synchronous mode, and transmit internal clock mode are set. The relationship between bit clock and
network clock is determined by DIV2, PSR, and PM bits. This feature is especially useful in I2S master
mode to output oversampling clock on SRCK port.
6–5
I2SMODE
0 Network clock not output on SRCK port.
1 Network clock output on SRCK port.
I2S Mode Select
These bits allow the I²S to operate in normal, I²S master or I²S slave mode.
00 Normal mode
01 I²S master mode
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1688
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.