K60P100M100SF2RM Datasheet, PDF (1747/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 54
General purpose input/output (GPIO)
54.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration chapter.
The general purpose input and output (GPIO) module interfaces to the processor core via
a zero wait state interface for maximum pin performance. Accesses of any data size are
supported to the GPIO registers.
The GPIO data direction and output data registers control the direction and output data of
each pin when the pin is configured for the GPIO function. The GPIO input data register
displays the logic value on each pin when the pin is configured for any digital function,
provided the corresponding port control and interrupt module for that pin is enabled.
Efficient bit banging of the general purpose outputs is supported through the addition of
set, clear and toggle write-only registers for each port output data register.
54.1.1 Features
• Rapid general purpose input and output
• Pin input data register visible in all digital pin-muxing modes
• Pin output data register with corresponding set/clear/toggle registers
• Pin data direction register
• Zero wait state access to GPIO registers
54.1.2 Modes of operation
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1747