K60P100M100SF2RM Datasheet, PDF (1021/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 39 FlexTimer (FTM)
The SWOCTRL register can be updated at each rising edge of system clock (SWOC = 0)
or by the enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1) according
to the following flowchart.
In the case of enhanced PWM synchronization, the SWOCTRL register synchronization
depends on SWSOC and HWSOC bits.
update SWOCTRL register at
each rising edge of system clock
no =
rising edge
of system
clock ?
= yes
update SWOCTRL
with its buffer value
begin
0 = _SWOC = 1
bit ?
update SWOCTRL register by
PWM synchronization
1 = _SYNCMODE = 0
bit ?
end
end
enhanced PWM synchronization
SWOCTRL is updated
by software trigger
1 = _SWSOC
bit ?
0=
SWSYNC
software
trigger
bit ?
=1
=0
end
update SWOCTRL
with its buffer value
end
0=
end
SWOCTRL is updated
by hardware trigger
HWSOC ^{= 1}
bit ?
hardware
trigger
TRIGn
bit ?
=0
=1
wait hardware trigger n
update SWOCTRL
with its buffer value
HWTRIGMODE ^{= 1}
bit ?
=0
clear TRIGn bit
end
Figure 39-219. SWOCTRL Register Synchronization Flowchart
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1021