K60P100M100SF2RM Datasheet, PDF (314/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
Register in the ARM core forces the MCU into VLPS and hardware sets the LPWUI
bit set.
In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR.
On transitions from VLPR to VLPS with LPLLSM set to 000b, hardware forces
LPLLSM to value of 010b.
A module capable of providing an asynchronous interrupt to the device (for example, an
enabled pin interrupt, NMI, RTC, UART wakeup on edge, CMP or ADC) takes the
device out of VLPS and returns the device to VLPR provided the LPWUI bit is clear.
If LPWUI is set, the device returns to normal run mode upon an interrupt request. The
REGONS bit must be set before allowing the system to return to a frequency higher than
allowed in VLPR.
An asserted RESET pin or a watchdog timeout causes VLPS exit. This returns the device
to normal run mode.
13.1.2.4.3 Low-Leakage Stop (LLS) Mode
Low leakage stop (LLS) mode can be entered from normal run or VLPR modes.
The MCU enters LLS mode if:
• In sleep-now or sleep-on-exit mode, the SLEEPDEEP bit is set in the System Control
Register in the ARM core, and
• The device is configured as per Table 13-2.
In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put
in a state-retention mode that does not allow them to operate while in LLS.
In LLS, configure the low leakage wake up (LLWU) module to enable the desired
wakeup sources. The available wakeup sources in LLS are detailed in the Chip
Configuration details for this device.
After wakeup from LLS, the device returns to normal run mode with a pending LLWU
module interrupt. In the LLWU interrupt service routine (ISR) poll the LLWU module
wakeup flags to determine the source of the wakeup.
NOTE
The LLWU interrupt must not be masked by the interrupt
controller to avoid a scenario where the system does not fully
exit stop mode on an LLS recovery.
An asserted RESET pin exits LLS. This returns the device to normal run mode. When
LLS is exiting via the RESET pin, the PIN and WAKEUP bits are set in the SRSL
register.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
314
Freescale Semiconductor, Inc.