K60P100M100SF2RM Datasheet, PDF (501/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 21 Direct Memory Access Controller (eDMA)
complete condition is indicated by both bits reading zero after the TCDn_CSR[START]
was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active
status may be missed if the channel execution is short in duration.
The TCD status bits execute the following sequence for a software activated channel:
Stage
1
2
3a
3b
START
1
0
0
0
TCDn_CSR bits
ACTIVE
0
1
0
0
DONE
0
0
0
1
State
Channel service request via software
Channel is executing
Channel has completed the minor loop and is idle
Channel has completed the major loop and is idle
The best method to test for minor-loop completion when using hardware, that is,
peripheral, initiated service requests is to read the TCDn_CITER field and test for a
change. The hardware request and acknowledge handshake signals are not visible in the
programmer's model.
The TCD status bits execute the following sequence for a hardware-activated channel:
Stage
1
2
3a
3b
START
0
0
0
0
TCDn_CSR bits
ACTIVE
0
1
0
0
DONE
0
0
0
1
State
Channel service request via hardware (peripheral
request asserted)
Channel is executing
Channel has completed the minor loop and is idle
Channel has completed the major loop and is idle
For both activation types, the major-loop-complete status is explicitly indicated via the
TCDn_CSR[DONE] bit.
The TCDn_CSR[START] bit is cleared automatically when the channel begins execution
regardless of how the channel activates.
21.5.5.2 Reading the transfer descriptors of active channels
The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES
values if read while a channel executes. The true values of the SADDR, DADDR, and
NBYTES are the values the eDMA engine currently uses in its internal register file and
not the values in the TCD local memory for that channel. The addresses, SADDR and
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
501