K60P100M100SF2RM Datasheet, PDF (532/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Watchdog Operation with 8-bit access
23.7.11 Watchdog Reset Count Register (WDOG_RSTCNT)
Address: WDOG_RSTCNT is 4005_2000h base + 14h offset = 4005_2014h
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RSTCNT
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WDOG_RSTCNT field descriptions
Field
15–0
RSTCNT
Description
Counts the number of times the watchdog resets the system. This register is reset only on a POR. Writing
1 to the bit to be cleared, enables you to clear the contents of this register.
23.7.12 Watchdog Prescaler Register (WDOG_PRESC)
Address: WDOG_PRESC is 4005_2000h base + 16h offset = 4005_2016h
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
PRESCVAL
Write
Reset 0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
WDOG_PRESC field descriptions
Field
15–11
Reserved
10–8
PRESCVAL
7–0
Reserved
Description
This read-only field is reserved and always has the value zero.
3-bit prescaler for the watchdog clock source. A value of zero indicates no division of the input WDOG
clock. The watchdog clock is divided by (PRESCVAL + 1) to provide the prescaled WDOG_CLK.
This read-only field is reserved and always has the value zero.
23.8 Watchdog Operation with 8-bit access
This section discusses 8-bit access considerations.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
532
Freescale Semiconductor, Inc.