K60P100M100SF2RM Datasheet, PDF (545/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 24 Multipurpose Clock Generator (MCG)
24.3.4 MCG Control 4 Register (MCG_C4)
Reset values for DRST and DMX32 bits are 0.
Address: MCG_C4 is 4006_4000h base + 3h offset = 4006_4003h
Bit
7
6
5
4
3
2
1
0
Read
Write
DMX32
DRST_DRS
FCTRIM
SCFTRIM
Reset
0
0
0
x*
x*
x*
x*
x*
* Notes:
• x = Undefined at reset.
• A value for FCTRIM is loaded during reset from a factory programmed location . x = Undefined at reset.
MCG_C4 field descriptions
Field
7
DMX32
Description
DCO Maximum Frequency with 32.768 kHz Reference
The DMX32 bit controls whether or not the DCO frequency range is narrowed to its maximum frequency
with a 32.768 kHz reference.
The following table identifies settings for the DCO frequency range.
NOTE: The system clocks derived from this source should not exceed their specified maximums.
DRST_DRS
00
01
10
11
DMX32
0
1
0
1
0
1
0
1
Reference Range FLL Factor
31.25-39.0625 kHz 640
32.768 kHz
732
31.25-39.0625 kHz 1280
32.768 kHz
1464
31.25-39.0625 kHz 1920
32.768 kHz
2197
31.25-39.0625 kHz 2560
32.768 kHz
2929
DCO Range
20-25 MHz
24 MHz
40-50 MHz
48 MHz
60-75 MHz
72 MHz
80-100 MHz
96 MHz
6–5
DRST_DRS
0 DCO has a default range of 25%.
1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
DCO Range Select
The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to
the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The
DRST field does not update immediately after a write to the DRS field due to internal synchronization
between clock domains. Refer to DCO Frequency Range table for more details.
00 Encoding 0 — Low range (reset default).
01 Encoding 1 — Mid range.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
545