K60P100M100SF2RM Datasheet, PDF (1738/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
Table 53-51. I²S bit clock and frame rate as a function of PSR, PM, and DIV2 (continued)
Bits/
word
16
16
16
Words/
frame
1
2
4
MCLK/network clock
freq (MHz)
11.2896
11.2896
11.2896
DIV2
0
0
0
TCCR
PSR PM WL DC
0
770
0
371
0
173
Bit clock
(kHz)
STCK
705.6
1411.2
2822.4
Frame
rate
(kHz)
44.1
44.1
44.1
The table below shows an example of programming clock controller divider ratios to
generate the appropriate oversampling clock and peripheral clock frequencies for various
sampling rates. In these examples, the master mode is selected either by setting I²S
master bit (CR[I2SMODE] = 01b) or individually programming the I²S in network,
synchronous, transmit internal mode. (The table specifically illustrates the I²S mode
frequencies/sample rates). The oversampling clock is network clock.
I²S master mode requires a 32-bit word length, regardless of the actual data type.
Consequently, the fixed I²S frame rate of 64 bits per frame (word length (TCCR[WL])
can be any value) and TCCR[DC] = 1 are assumed.
Table 53-52. I²S system clock, bit clock, frame clock in master mode
Sampling/frame _{Over- sampling}
rate (kHz)
rate
44.10
384
22.05
384
MCLK/network
clock
freq (MHz)
16.934
16.934
TCCR
DIV2
PS
R
PM
0
02
0
05
Bit clk (kHz)
STCK
2822.33
1411.17
11.025
384
16.934
0
0 11
705.58
48.00
256
12.288
0
01
3072
53.4.3 External frame and clock operation
When applying external frame sync and clock signals to I²S, there should be at least four
bit-clock cycles between the enabling of the transmit or receive section and the rising
edge of the corresponding frame sync signal. The transition of TFS or RFS should be
synchronized with the rising edge of external clock signal, STCK or SRCK.
1738
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.