K60P100M100SF2RM Datasheet, PDF (1474/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization/Application Information
Clear IICIF
Y
SLTF or
N
SHTF2=1?
Y
Tx
Rx
Tx/Rx?
Last byte
Y
transmitted?
Last byte
Y
to be read?
N
N
N
FACK=1?
Y
Master
N
mode?
See typical I2C
interrupt routine
flow chart
Y
Clear ARBL
Arbitration
lost?
N
N
RXAK=0?
Y
Y
End of
address cycle
(master Rx)?
N
Clear IICIF
Write next
byte to Data reg
Y
2nd to
last byte to be
read?
N
Delay (note 2)
Read data from
Data reg
and soft CRC
Delay (note 2)
Read data and
Soft CRC
Set TXAK to
proper value
Delay (note 2)
Set TXACK=1
Clear FACK=0
Generate stop
signal (MST=0)
Set TXAK to
proper value
N
IAAS=1?
Y
IAAS=1?
Y
(read)
Y
Address transfer
see note 1
SRW=1?
Rx
N (write)
N
Tx/Rx?
Tx
Delay (note 2)
Read data from
Data reg
and soft CRC
Set TXAK to
proper value
Clear IICIF
Delay (note 2)
Delay (note 2)
Read data from
Data reg
and soft CRC
ACK from
receiver?
N
Y
Clear IICIF
Transmit
next byte
Switch to
Rx mode
Clear IICIF
Delay (note 2)
Set Tx mode
Set TXAK to
proper value
Clear IICIF
Delay (note 2)
Switch to
Rx mode
Dummy read
from Data reg
Generate stop
signal (MST=0)
Read data from
Data reg
and store
Write data
to Data reg
Read data from
Data reg
and store
Dummy read
from Data reg
RTI
Notes:
1. If general call or SIICAEN is enabled, check to determine if the received address is a general call address (0x00) or an SMBus
device default address. In either case, they must be handled by user software.
2. In receive mode, one bit time delay may be needed before the first and second data reading.
Figure 50-43. Typical I2C SMBus Interrupt Routine
1474
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.