K60P100M100SF2RM Datasheet, PDF (89/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

RGD0_WORD0
RGD0_WORD1
RGD0_WORD2
RGD0_WORD3
RGDAAC0
Chapter 3 Chip Configuration
Table 3-20. Reset Values for RGD0 Registers
Register
0000_0000h
FFFF_FFFFh
0061_F7DFh
0000_0001h
0061_F7DFh
Reset value
3.3.7.5 Write Access Restrictions for RGD0 Registers
In addition to configuring the initial state of RGD0, the MPU implements further access
control on writes to the RGD0 registers. Specifically, the MPU assigns a priority scheme
where the debugger is treated as the highest priority master followed by the core and then
all the remaining masters.
The MPU does not allow writes from the core to affect the RGD0 start or end addresses
nor the permissions associated with the debugger; it can only write the permission fields
associated with the other masters.
These protections (summarized below) guarantee that the debugger always has access to
the entire address space and those rights cannot be changed by the core or any other bus
master.
Table 3-21. Write Access to RGD0 Registers
Core
Bus Master
Write Access?
Partial. The Core cannot write to the following registers or
register fields:
• RGD0_WORD0, RGD0_WORD1, RGD0_WORD3
• RGD0_WORD2[M1SM, M1UM]
• RGDAAC0[M1SM, M1UM]
Debugger
All other masters
NOTE: Changes to the RGD0_WORD2 alterable fields
should be done via a write to RGDAAC0.
Yes
No
3.3.8 Peripheral Bridge Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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