K60P100M100SF2RM Datasheet, PDF (899/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 37 Voltage Reference (VREFV1)
• Bandgap enabled/standby (output buffer disabled)
• Tight-regulation buffer mode (output buffer enabled)
• 1.2 V output at room temperature
• Dedicated output pin, VREF_OUT
• Load regulation in tight-regulation mode
37.1.3 Modes of Operation
The Voltage Reference continues normal operation in Run, Wait, and Stop modes. The
Voltage Reference can also run in Very Low Power Run (VLPR), Very Low Power Wait
(VLPW) and Very Low Power Stop (VLPS). The VREF regulator is not available in any
Very Low Power modes and must be disabled (SC[REGEN]=0) before entering these
modes. Note however that the accuracy of the output voltage will be reduced (by as much
as several mVs) when the VREF regulator is not used.
NOTE
The assignment of module modes to core modes is chip-
specific. For module-to-core mode assignments, see the chapter
that describes how modules are configured.
37.1.4 VREF Signal Descriptions
The following table shows the Voltage Reference signals properties.
Table 37-1. VREF Signal Descriptions
Signal
Description
I/O
VREF_OUT
Internally-generated Voltage Reference output
O
NOTE
• In Disable mode, the status of the VREF_OUT signal is
high-impedence.
37.2 Memory Map and Register Definition
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
899