K60P100M100SF2RM Datasheet, PDF (105/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 3 Chip Configuration
Cortex-M4
core
Crossbar
switch
MPU
MPU
Transfers
SRAM upper
SRAM lower
Figure 3-24. SRAM configuration
Table 3-37. Reference links to related information
Topic
Full description
System memory map
Clocking
Transfers
Related module
SRAM
SRAM controller
ARM Cortex-M4 core
Memory protection unit
Reference
SRAM
System memory map
Clock Distribution
SRAM controller
ARM Cortex-M4 core
Memory protection unit
3.5.3.1 SRAM sizes
This device contains SRAM tightly coupled to the ARM Cortex-M4 core. The amount of
SRAM for the devices covered in this document is shown in the following table.
Device
MK60DN256ZVLL10
MK60DX256ZVLL10
MK60DN512ZVLL10
SRAM (KB)
64
64
128
3.5.3.2 SRAM Arrays
The on-chip SRAM is split into two equally-sized logical arrays, SRAM_L and
SRAM_U.
The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a
contiguous block in the memory map. As such:
• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending
address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning
address.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
105