K60P100M100SF2RM Datasheet, PDF (1131/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

44.1.3 Block Diagram
Receive
FIFO
TCP offload
engine (TOE)
functions
TCP/IP
performance
optimization
Chapter 44 10/100-Mbps Ethernet MAC (ENET)
MAC
RX control
CRC
check
Pause frame
terminate
Transmit
FIFO
TCP/IP
performance
optimization
TX control
CRC
generate
Pause frame
generate
Configuration
statistics
MDIO
master
Register interface
Figure 44-1. 10/100 Ethernet MAC-NET Core Block Diagram
44.2 External Signal Description
MII
MII_COL
MII_CRS
MII_MDC
RMII
—
—
Description
I/O
Asserted upon detection of a I
collision and remains
asserted while the collision
persists. This signal is not
defined for full-duplex mode.
Carrier sense. When
I
asserted, indicates transmit
or receive medium is not idle.
RMII_MDC
In RMII mode, this signal is
present on the
RMII_CRS_DV pin.
Output clock provides a
O
timing reference to the PHY
for data transfers on the
MDIO signal.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1131