K60P100M100SF2RM Datasheet, PDF (317/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 13 Mode Controller
• Computer operating properly (COP) timer
• Clock generator (MCG) loss of clock reset (LOC)
• Low-voltage detect (LVD)
• Wakeup from very low leakage stop modes, VLLSx
• Software reset (SW) - by setting SYSRESETREQ bit of the NVIC's Application
Interrupt and Reset Control Register
• LOCKUP - core in lockup state
• EzPort
• MDM AP Reset - by setting System Reset Request bit of the MDM AP Control
Register
Debug reset:
• Asserting JTAG_TRST pin
Each of the system reset sources, with the exception of the EzPort and MDM AP reset,
has an associated bit in the system reset status low (SRSL) register.
13.1.3.1 Power-On Reset (POR)
When power is initially applied to the device, or when the supply voltage drops below the
power-on-reset re-arm voltage level (V_POR), the POR circuit causes a reset condition. As
the supply voltage rises, the LVD circuit holds the MCU in reset until the supply rises
above the LVD low threshold (V_LVDL). The POR and LVD bits in SRSL are set
following a POR.
13.1.3.2 External RESET Pin
RESET is a dedicated pin. This pin is open drain and has an internal pullup device.
Asserting RESET resets the device from any run, wait, stop, VLP, LLS, or VLLS mode.
When the RESET pin is the cause of reset, the SRSL[PIN] bit is set.
13.1.3.3 Computer Operating Properly (COP) Timer Reset
The watchdog timer monitors the operation of the system by expecting periodic
communication from the software. Generally, this is known as servicing, or refreshing,
the watchdog. If this periodic refreshing does not occur, the watchdog issues a system
reset. When the watchdog timer expiration causes a reset, the SRSL[COP] bit is set.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
317