K60P100M100SF2RM Datasheet, PDF (1453/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 50 Inter-Integrated Circuit (I2C)
50.3.6 I2C Control Register 2 (I2Cx_C2)
Addresses: I2C0_C2 is 4006_6000h base + 5h offset = 4006_6005h
I2C1_C2 is 4006_7000h base + 5h offset = 4006_7005h
Bit
Read
Write
Reset
7
GCAEN
0
6
ADEXT
0
5
HDRS
0
4
SBRC
0
3
RMEN
0
2
1
0
AD[10:8]
0
0
0
I2Cx_C2 field descriptions
Field
7
GCAEN
General call address enable
Enables general call address.
Description
6
ADEXT
0 Disabled
1 Enabled
Address extension
Controls the number of bits used for the slave address.
5
HDRS
0 7-bit address scheme
1 10-bit address scheme
High drive select
Controls the drive capability of the I2C pads.
4
SBRC
0 Normal drive mode
1 High drive mode
Slave baud rate control
Enables independent slave mode baud rate at max frequency. This forces clock stretching on SCL in very
fast I2C modes.
3
RMEN
0 The slave baud rate follows the master baud rate and clock stretching may occur
1 Slave baud rate is independent of the master baud rate
Range address matching enable
This bit controls slave address matching for addresses between the values of the A1 and RA registers.
When this bit is set, a slave address match occurs for any address greater than the value of the A1
register and less than or equal to the value of the RA register.
2–0
AD[10:8]
0 Range mode disabled. No address match occurs for an address within the range of values of the A1
and RA registers.
1 Range mode enabled. Address matching occurs when a slave receives an address within the range
of values of the A1 and RA registers.
Slave address
Contains the upper three bits of the slave address in the 10-bit address scheme. This field is valid only
when the ADEXT bit is set.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1453