K60P100M100SF2RM Datasheet, PDF (94/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

System modules
Table 3-24. DMA request sources - MUX 0 (continued)
Source
number
61
62
63
Source module
DMA MUX
DMA MUX
DMA MUX
Source description
Always enabled
Always enabled
Always enabled
1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel.
3.3.9.2 DMA transfers via PIT trigger
The PIT module can trigger a DMA transfer on the first four DMA channels. The
assignments are detailed at PIT/DMA Periodic Trigger Assignments .
3.3.10 DMA Controller Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge 0
Register
access
Transfers
DMA Controller
Requests
Topic
Full description
System memory map
Register access
Clocking
Power management
Transfers
Figure 3-14. DMA Controller configuration
Table 3-25. Reference links to related information
Related module
DMA Controller
Peripheral bridge
(AIPS-Lite 0)
Crossbar switch
Reference
DMA Controller
System memory map
AIPS-Lite 0
Clock distribution
Power management
Crossbar switch
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
94
Freescale Semiconductor, Inc.