K60P100M100SF2RM Datasheet, PDF (1134/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
Absolute
address
(hex)
ENET memory map
Register name
Width
(in bits)
Access
Reset value
400C_0004 Interrupt Event Register (ENET_EIR)
32
w1c 0000_0000h
400C_0008 Interrupt Mask Register (ENET_EIMR)
32
R/W 0000_0000h
400C_0010 Receive Descriptor Active Register (ENET_RDAR)
32
R/W 0000_0000h
400C_0014 Transmit Descriptor Active Register (ENET_TDAR)
32
R/W 0000_0000h
400C_0024 Ethernet Control Register (ENET_ECR)
32
R/W F000_0000h
400C_0040 MII Management Frame Register (ENET_MMFR)
32
R/W 0000_0000h
400C_0044 MII Speed Control Register (ENET_MSCR)
32
R/W 0000_0000h
400C_0064 MIB Control Register (ENET_MIBC)
32
R/W C000_0000h
400C_0084 Receive Control Register (ENET_RCR)
32
R/W 05EE_0001h
400C_00C4 Transmit Control Register (ENET_TCR)
32
R/W 0000_0000h
400C_00E4 Physical Address Lower Register (ENET_PALR)
32
R/W 0000_0000h
400C_00E8 Physical Address Upper Register (ENET_PAUR)
32
R/W 0000_8808h
400C_00EC Opcode/Pause Duration Register (ENET_OPD)
32
R/W 0001_0000h
400C_0118 Descriptor Individual Upper Address Register (ENET_IAUR) 32
R/W 0000_0000h
400C_011C Descriptor Individual Lower Address Register (ENET_IALR) 32
R/W 0000_0000h
400C_0120 Descriptor Group Upper Address Register (ENET_GAUR)
32
R/W 0000_0000h
400C_0124 Descriptor Group Lower Address Register (ENET_GALR)
32
R/W 0000_0000h
400C_0144 Transmit FIFO Watermark Register (ENET_TFWR)
32
R/W 0000_0000h
400C_0180 Receive Descriptor Ring Start Register (ENET_RDSR)
32
400C_0184
Transmit Buffer Descriptor Ring Start Register
(ENET_TDSR)
32
Table continues on the next page...
R/W 0000_0000h
R/W 0000_0000h
Section/
page
44.3.1/
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44.3.3/
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44.3.4/
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44.3.5/
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44.3.7/
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44.3.8/
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44.3.9/
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44.3.10/
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44.3.11/
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44.3.12/
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.